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An open-source agent flow from natural language spec through Verilog RTL and UVM verification to front-end signoff on commercial EDA tools

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ai-agentschip-designclaude-codeclaude-code-plugindshdsh-pluginhardware-verificationopencodertl-designsystemveriloguvmverilog
Language
Python
License
MIT License
Size
5.2 MB
Created
Jun 11, 2026
Last Updated
Sep 2, 2026
Last Pushed
Aug 30, 2026

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